Inter-Integrated Circuit (IIC) popularly known in the market as I²C or I2C is the most basic communication protocol used in the industries for on-board communications among the peripherals mounted over the PCB. This protocols' intellectual property was managed by Philips Semiconductors which later got divested into a consortium of financers and got a new name as Next eXPerience (NXP) and established as NXP Semiconductors. So, this technology is basically coming from a Netherlands based company where local culture is a Dutch speaking community.
In context to Post Silicon Verification/ Application:
Technically, you will find a lot of information, explanation, figures and demonstrations, also manual from the source company. To summarise the activities followed in I2C and topics a learner should look into are discussed further over here. As per the manual I2C supports 5 modes which decides the speed of the communication. These are given as:
- Standard Mode with max. speed of 100kbps.
- Fast Mode with max. speed of 400kbps.
- Fast Mode Plus with max. speed of 1Mbps.
- High Speed mode with max. speed of 3.4Mbps.
- Ultra fast mode with max. speed of 5Mbps which is supported in a unilateral fashion. This means that protocol is implemented for write only from 'master' to 'slave' only while configured using push-pull drivers only. So, this mode has constraints which makes it a special use case to achieve ultra fast speed.
This communication is known to be achieved by two parties sender and receiver where any one of the party controls the communication known as Master and another one will be called as Slave. This communication is handled by the master over a two wire communication namely 'serial-clock' i.e., SCL and 'serial-data' i.e., SDA. Frame format and waveforms for this communication could be searched over internet or could be looked into the manual. Conceptually, a brief overview is discussed here.
For starting the basic communication,
- 'START Condition' is generated over the I2C bus i.e., SDA is pulled low when SCL is high.
- Master writes 7 bit slave address onto the I2C bus which is con-catenated with read(1) / write(0) bit making it an 8-bit information from the 'master' side.
- Then the I2C logic releases the control from the master to slave. The reason is that slave has to acknowledge the reception of the address code received from the master. The slave in its response will keep the SCL pulled to low in order to signal the master that it had received the address and it matches to its slave address and it is ready to consider further communication as directed by 'master'. This creates the Acknowledge (ACK)/ Not Acknowledgement (NACK) at the 9th bit in the communication chunk of data.
- In the experience of the writer, this is the place where master writes the offset address to be accessed at the particular memory location of the EEPROM connected to the master processor.
- Also, there is a feature of 10 bit addressing where an established method of address sequencing is defined and could be used. Refer to manual for this activity.
- After this, as per the read/ write bit written by master above, further communication of read or write activity is followed where each communication holds a chunk of 8 bit data followed by ACK (0)/ NACK (1) bit.
- 'Stop condition' is generated when there is NACK or 'master' generates stop condition by pulling SDA High when SCL is high.
Most Significant Bit (MSB) is transmitted first in I2C. There is a feature of 'General Broadcast' where all the slaves are given data simultaneously.
Below is an excerpt generated from ChatGPT to brief an idea for clock-stretching and ultra-fast mode supported by modern processors / micro-controllers:
FEATURES:
In I²C, the correct term is actually clock stretching, not "bit stretching" — but it's understandable to mix them up. Here's a clear explanation:
🕒 What is Clock Stretching in I²C?
Clock stretching is a feature in I²C that allows a slave device to hold the clock line (SCL) low to signal the master to wait. This happens when the slave needs more time to process data or get ready to send/receive it.
🔁 How It Works:
-
The master generates the clock on the
SCLline. - The slave may pull
SCLlow during a clock pulse to delay the master's next clock edge. - The master must monitor
SCL, and wait until the slave releases it (allows it to go high) before continuing.
📌 Why It's Needed:
- A slave might not be fast enough to respond immediately.
Used when:
- Reading from slow memory
- Processing internal data
- Handling interrupts
🔍 Visual Representation:
Master sets SCL high ---> Slave holds SCL low --> Master waits
This prevents data corruption by ensuring the master doesn’t continue until the slave is ready.
🧠 Example Use Case:
Imagine an EEPROM or a sensor that needs a few microseconds to fetch data. If the master sends a read request and immediately starts reading, it may get garbage data. Clock stretching gives the slave a chance to prepare the correct response.
⚠️ Important Notes:
- Not all I²C masters support clock stretching (especially some basic microcontrollers).
- If unsupported and the slave stretches the clock, the system may fail or lock up.
- This mechanism applies to the SCL line, not SDA.
ULTRA-FAST MODE: A SPECIAL CASE in I2C
⚡ Ultra-Fast Mode (UFm) in I²C – Explained
Ultra-Fast Mode (UFm) is a special, high-speed variation of the I²C protocol defined by NXP (formerly Philips). It allows data rates of up to 5 Mbps, compared to:
| I²C Mode | Max Speed |
|---|---|
| Standard Mode | 100 kbps |
| Fast Mode | 400 kbps |
| Fast Mode Plus | 1 Mbps |
| Ultra-Fast Mode | 5 Mbps |
🔧 Key Characteristics of UFm:
| Feature | Description |
|---|---|
| Speed | Up to 5 Mbps |
| Direction | Write-only from master to slave (no read from slave) |
| Open-drain lines? | No – Uses push-pull drivers |
| SDA/SCL line behavior | Fast rise/fall times due to push-pull |
| Clock stretching | ❌ Not supported |
| Start/Stop conditions | Same as regular I²C |
| Acknowledgement (ACK) | ❌ No ACK/NACK after each byte |
🚫 Limitations:
- No read capability – only master → slave communication is possible.
- No error checking – without ACK/NACK, the master doesn’t know if the slave received the data correctly.
- Not suitable for multi-master systems or where reliable data delivery is critical.
📦 When to Use Ultra-Fast Mode:
UFm is ideal for situations where:
- Only unidirectional high-speed data transmission is required.
- The system is tightly controlled (e.g., embedded systems with a trusted slave).
- Minimal bus traffic and timing simplicity are more important than error-checking.
✅ Use Cases:
- High-speed data dump to a display
- Streaming large data to memory-mapped peripherals (like DACs)
- Sensor arrays where slaves don’t need to respond
🧠 Summary:
| Feature | UFm I²C |
|---|---|
| Max Speed | 5 Mbps |
| Communication | Master → Slave only |
| Electrical Driver | Push-pull |
| ACK/NACK | Not used |
| Clock Stretching | Not allowed |
| Use Case | High-speed, simple, write-only communication |
Below is an excerpt from manual for Ultra Fast Mode (UFm):
Since UFm I2C-bus uses push-pull drivers, it does not have the multi-controller capability of the wired-AND open-drain Sm (Standard mode), Fm (Fast mode), and Fm+ (Fast mode+) I2C-buses. In UFm, a controller is the only device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. All other devices addressed are considered targets.
Feature of multi-master and arbitration:
In I²C, multi-master and arbitration are two important features that allow multiple master devices to share the same bus without causing data collisions or corruption.
🧰 1. Multi-Master Feature
Definition:
In I²C, multiple masters can be connected to the same SCL and SDA lines and can initiate communication independently.
Purpose:
- Allows several controllers (masters) to communicate with the same or different slave devices on the same bus.
- Useful in complex systems like SoCs, where different modules may take control of the bus at different times.
Key Requirements for Multi-Master:
- Bus idle detection before starting communication.
- Arbitration logic to resolve conflicts when two masters start communication at the same time.
- All devices must support clock synchronization (built into I²C).
⚔️ 2. Arbitration Mechanism
Definition:
Arbitration is the conflict resolution mechanism when two or more masters try to access the I²C bus simultaneously.
🔄 How Arbitration Works:
- Both masters monitor the SDA line while sending data.
- Data is transferred bit-by-bit.
- If a master tries to send a high (1) but sees a low (0) (another master is pulling it down), it loses arbitration and backs off.
- The master that continues matching bits remains active.
It’s based on the fact that SDA is open-drain, so a ‘0’ wins over a ‘1’.
✅ Example:
| Master A sends: | 1010000 (address of slave A) |
|---|---|
| Master B sends: | 1001000 (address of slave B) |
- Both send
1→ OK - Both send
0→ OK - A sends
1, B sends0→ A sees a0, so A loses arbitration
⚠️ Important Points:
- Arbitration is non-destructive: The winning master continues seamlessly.
- Only works because of open-drain lines and SDA line monitoring.
- Applies to both address and data phase (if another master begins sending during an ongoing transaction).
🧠 Summary Table:
| Feature | Description |
|---|---|
| Multi-Master | Multiple controllers (masters) on one I²C bus |
| Arbitration | Real-time conflict resolution using bit-by-bit monitoring |
| Bus Sharing | All masters share the same SCL and SDA lines |
| Priority | Based on address/data being transmitted – first differing bit |
| Clock Sync | I²C masters synchronize their SCL line – slowest master determines speed |
Topics to explore further:
